The Memory Hierarchy

• Faster memory is more expensive than slower memory.
• For the best performance at the lowest cost, memory is organized in a
hierarchical fashion.
• Small, fast storage elements are kept in the CPU, larger, slower main memory
is accessed through the data bus.
• Larger, (almost) permanent storage in the form of disk and tape drives is still
further from the CPU.
• An entire blocks of data is copied after a hit because the principle of
locality tells us that once a byte is accessed, it is likely that a
nearby data element will be needed soon.
• There are three forms of locality:
– Temporal locality- Recently-accessed data elements tend to be
accessed again.
– Spatial locality - Accesses tend to cluster.
– Sequential locality - Instructions tend to be accessed
sequentially.
• Cache Line -- The number of bytes brought in with this block
Mechanism:
• To access a particular piece of data, the CPU sends a request to its
nearest memory, usually cache.
• If the data is not in cache, then main memory is queried. If the data is
not in main memory, then the request goes to disk.
• Once the data is located, the data,
SDRAM; Random Access Memory
• Short for Synchronous DRAM, a type of DRAM that can run at much
higher clock speeds than conventional memory. SDRAM actually
synchronizes itself with the CPU's bus and is capable of running at 133
MHz,
DDR (Double Data Rate) is a technology used in some SDRAM memories
to increase the speed at which data can be written/retrieved from the
memory.
DDR increase the transfer rate by sending/receiving memory data twice
per clock cycle. This give a theoretical multiplication of transfer speed by
two.
DDR2-SDRAM maintains the same core functions, transferring 64 bits of data twice
every clock cycle for an effective transfer rate twice that of the front-side bus
(FSB) of a computer system, and an effective bandwidth equal to its speed x 8.
Flash Memory
A type of EEPROM.
Non-volatile – doesn’t require power to
hold data.
Data is written in blocks - not byte
accessible. Great for disk-like devices
requiring 4096 bytes to be read/written;
not good for Random Access Memory.
Limited to 1,000,000 cycles – and blocks
can go bad.
The controller can do bad block remapping
and error checking.
The controller can do wear leveling –
moving blocks around so that no one
area on the chip has excessive wear.